;=================================================================================
; SMDKV210 System Init CMM File : <SMDKV210_SystemInit.cmm>
; - Initialize SRAM/DRAM/Clock controller
;
;                            2008.10.27 / by AP Dev.System LSI.Samsung Electronics
;=================================================================================

;*********************************************************************************
; Initialize SRAM/DRAM/Clock controller (OPTIONAL)
;*********************************************************************************
; [ Definition of Basic Operation Mode ]


;---------------------------------------------------------------------------------
; SRAM Initialization                                              
;---------------------------------------------------------------------------------
 print "setting SRAM"

&DDR='g'
&LPDDR='h'
&DDR2='i'
&LPDDR2='j'
&DMC_en='1'
&MCP_AC_TYPE='a'
&MCP_H_TYPE='b'

&DRAM_INIT=&DMC_en
&DRAM_TYPE=&DDR2

&SILICON=1 ; FPGA = 0, Silicon = 1
&USE_PLL=1 

IF &SILICON==1 
(
 IF &USE_PLL==1
 (
;;;; Sillicon
	; Set Mux to FIN
	d.s ASD:0xE0100200 %LE %LONG 0x00000000 ; CLK_SRC0

	; Disable PLL
	d.s ASD:0xE0100100 %LE %LONG 0x00000000 ; APLL_CON
	d.s ASD:0xE0100108 %LE %LONG 0x00000000 ; MPLL_CON
	;d.s ASD:0xE0100110 %LE %LONG 0x00000000 ; EPLL_CON
	;d.s ASD:0xE0100120 %LE %LONG 0x00000000 ; VPLL_CON

	;######### Bus clock Divider table ##########
	;# * CLK_DIV0 = 0xE0100300 
	;# 0x PCLKP HCLKP PCLKD HCLKD PCLKM HCLKM DIVA2M ARMDIV => register config, use 3 or 4 bit
	;# 0x   0     0     0     0     0     0     0     0   
	;#
	;# 0x14131330 ; -> 1:1:4:4, 1:4:5 (APLL:ARMCLK:DIVA2M:HCLKMSYS, MPLL:HCLKDSYS:HCLKPSYS), PCLKdiv is 1/2 for all bus
	;# 0x13131330 ; -> 1:1:4:4, 1:4:4 
	;# 0x14141220 ; -> 1:1:3:3, 1:5:5 
	;# 0x14131440 ; -> 1:1:5:5, 1:4:5 
	;# 0x10101110 ; -> 1:1:2:2, 1:1:1 
	;# 0x14131111 ; -> 1:2:4:4, 1:4:5 
	;# 0x14131221 ; -> 1:2:6:6, 1:4:5 
	;# 0x14131331 ; -> 1:2:8:8, 1:4:5 
	
	;######### APLL MPS table ##########
	;# * APLL_CON = 0xE0100100 
	;# 0x EN..[31] MDIV[25:16] PDIV[13:8] SDIV[2:0]
	;# 0x   00        00         00        00   
	;#
	;# 0x80FA0601 ; -> 1000MHz 
	;# 0x80C80601 ; -> 800MHz 
	;# 0x80640401 ; -> 600MHz
	;# 0x80C80603 ; -> 200MHz
	;# 0x815B1001 ; -> 833MHz 
	;# 0x81851401 ; -> 667MHz
	;# 0x82152401 ; -> 533MHz

	;######### MPLL MPS table ##########
	;# * MPLL_CON = 0xE0100108 
	;# 0x EN..[31] MDIV[25:16] PDIV[13:8] SDIV[2:0]
	;# 0x   00        00         00        00   
	;#
	;# 0x829B1201 ; -> 667MHz 
	;# 0x89900602 ; -> 400MHz 

	;################### User config part ####################
	; Normal Clock Setting (800:200:166:133 = ARMCLK:HCLKMSYS:HCLKDSYS:HCLKPSYS)
	; Set Divider, APLL, MPLL
	d.s ASD:0xE0100300 %LE %LONG 0x14131330 ; -> 1:1:4:4, 1:4:5 
	d.s ASD:0xE0100100 %LE %LONG 0x80C80601 ; -> 800MHz 
	d.s ASD:0xE0100108 %LE %LONG 0x829B0C01 ; -> 667MHz 

	; High Clock Setting (1000:200:166:133 = ARMCLK:HCLKMSYS:HCLKDSYS:HCLKPSYS)
	; Set Divider, APLL, MPLL
	;d.s ASD:0xE0100300 %LE %LONG 0x14131440 ; -> 1:1:5:5, 1:4:5 
	;d.s ASD:0xE0100100 %LE %LONG 0x80FA0601 ; -> 1000MHz 
	;d.s ASD:0xE0100108 %LE %LONG 0x829B0C01 ; -> 667MHz 

	; Mid Clock Setting (667:166:166:133 = ARMCLK:HCLKMSYS:HCLKDSYS:HCLKPSYS)
	; Set Divider, APLL, MPLL
	;d.s ASD:0xE0100300 %LE %LONG 0x14131330 ; -> 1:1:4:4, 1:4:5 
	;d.s ASD:0xE0100100 %LE %LONG 0x81850E01 ; -> 667MHz 
	;d.s ASD:0xE0100108 %LE %LONG 0x829B0C01 ; -> 667MHz 

	; Low Clock Setting (533:133:100:100 = ARMCLK:HCLKMSYS:HCLKDSYS:HCLKPSYS)
	; Set Divider, APLL, MPLL
	;d.s ASD:0xE0100300 %LE %LONG 0x13131330 ; -> 1:1:4:4, 1:4:4 
	;d.s ASD:0xE0100100 %LE %LONG 0x82151201 ; -> 533MHz 
	;d.s ASD:0xE0100108 %LE %LONG 0x89900602 ; -> 400MHz 
	;#########################################################

	d.s ASD:0xE0100110 %LE %LONG 0x80600602 ; EPLL -> 96MHz
	d.s ASD:0xE0100120 %LE %LONG 0x806c0603 ; VPLL -> 54MHz

	wait 0.3s

	; Set Mux to PLL (Bus clock)
	d.s ASD:0xE0100200 %LE %LONG 0x10001111 ; CLK_SRC0 PLLsel -> APLLout(MSYS), MPLLout(DSYS,PSYS), EPLLout, VPLLout 
	
	if &DRAM_TYPE==&MCP_AC_TYPE 
	(
	; OneDRAM(DMC0) clock setting (divider & source mux) using MPLL
	d.s ASD:0xE0100218 %LE %LONG 0x01000000 ; CLK_SRC6[25:24] -> OneDRAM clock sel = MPLL 
	d.s ASD:0xE0100318 %LE %LONG 0x30000000 ; CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 
	)

	if &DRAM_TYPE==&DDR2 
	(
	; OneDRAM(DMC0) clock setting (divider & source mux) using MPLL
	d.s ASD:0xE0100218 %LE %LONG 0x00000000 ; CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M(@200Mhz), 01:SCLKMPLL
	d.s ASD:0xE0100318 %LE %LONG 0x00000000 ; CLK_DIV6[31:28] -> 0=1/1
	)
		
	; CLK OUT Setting
	; DIVVAL[23:20], CLKSEL[16:12]
	d.s ASD:0xE0100500 %LE %LONG 0x00909000 ; DIV=10, HCLK_MSYS

 )
)

;----------------------------------------------------------------------;
; SRAM/ROM Initialization                                              ;
;----------------------------------------------------------------------;
print "setting SRAM"

d.s ASD:0xE0200260 %LE %LONG 0x00444444 ; GPJ1 SROM_ADDR_16to21
d.s ASD:0xE02002C0 %LE %LONG 0x00040000 ; GPJ4 SROM_ADDR_16to21
d.s ASD:0xE8000000 %LE %LONG 0x0000000B ; CS0 - 16bit sram, enable nBE, Byte base address

;----------------------------------------------------------------------;
; OneDram Async Initialization                                              ;
;----------------------------------------------------------------------;
if &DRAM_TYPE==&MCP_AC_TYPE
(
	d.s ASD:0xE0106208 %LE %LONG 0x00000000 ; 0 : SCLK_ONEDRAM, 1 : HCLK200
	d.s ASD:0xF1E00000 %LE %LONG 0x00000000 ; 0 = Using 1 cycle synchronize, 1 = Using 1/2 cycle synchronizer
	d.s ASD:0xF1E0000C %LE %LONG 0x00000000 ; 0: Asynchronous mode, 1: Synchronous mode
)
if &DRAM_TYPE==&MCP_H_TYPE
(
	d.s ASD:0xE0106208 %LE %LONG 0x00000000 ; 0 : SCLK_ONEDRAM, 1 : HCLK200
	d.s ASD:0xF1E00000 %LE %LONG 0x00000000 ; 0 = Using 1 cycle synchronize, 1 = Using 1/2 cycle synchronizer
	d.s ASD:0xF1E0000C %LE %LONG 0x00000000 ; 0: Asynchronous mode, 1: Synchronous mode
)
if &DRAM_TYPE==&DDR2
(
    d.s ASD:0xE0106208 %LE %LONG 0x00000000 ; 0 : SCLK_ONEDRAM, 1 : HCLK200
    d.s ASD:0xF1E00000 %LE %LONG 0x00000000 ; 0 = Using 1 cycle synchronize, 1 = Using 1/2 cycle synchronizer
    d.s ASD:0xF1E0000C %LE %LONG 0x00000000 ; 0: Asynchronous mode, 1: Synchronous mode
)

;----------------------------------------------------------------------;
; DMC Drive Strength (defautl 2X -> Setting 4X)                                             ;
;----------------------------------------------------------------------;
;[DMC0]
d.s ASD:0xE02003CC %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE02003EC %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020040C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020042C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020044C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020046C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020048C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE02004AC %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE02004CC %LE %LONG 0x00003FFF ; 
;[DMC1]
d.s ASD:0xE02004EC %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020050C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020052C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020054C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020056C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE020058C %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE02005AC %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE02005CC %LE %LONG 0x0000FFFF ; 
d.s ASD:0xE02005EC %LE %LONG 0x00003fff ; 

;------------------------------------------------------------------------------;
; DRAM initialization                                                          ;
;------------------------------------------------------------------------------;
if &DRAM_INIT==&DMC_en
(
	print "SDRAM DMC0 Initialization"
	
	;;; dll enable
	d.s ASD:0xf0000018 %LE %LONG 0x00101000	;PhyControl0	DLL parameter setting, manual 0x00101000
	d.s ASD:0xf000001C %LE %LONG 0x00000086	;PhyControl1	DLL parameter setting, DDR2 Case
	;;;d.s ASD:0xf0000020 %LE %LONG 0x00000000	;PhyControl2	DLL parameter setting
	d.s ASD:0xf0000018 %LE %LONG 0x00101002	;PhyControl0	DLL on
	d.s ASD:0xf0000018 %LE %LONG 0x00101003	;PhyControl0	DLL을 start 시킴
	;;;d.s ASD:0xf0000040 %LE %LONG 0xXXXXXXX3	;PhyStatus0	DLL이 locking 되었는지 check
	wait 0.2s
	;; DLL Always ON
	d.s ASD:0xf0000018 %LE %LONG 0x82101003	;PhyControl0	DLL off시를 위해 locking value 를 forcing 시킴
	d.s ASD:0xf0000018 %LE %LONG 0x82101009	;PhyControl0	DLL off

	;;; dll disable
	;d.s ASD:0xf0000018 %LE %LONG 0x00000000	;PhyControl0	DLL parameter setting
	;d.s ASD:0xf000001C %LE %LONG 0x00000000	;PhyControl1	DLL parameter setting
	;d.s ASD:0xf0000020 %LE %LONG 0x00000000	;PhyControl2	DLL parameter setting

	if &DRAM_TYPE==&DDR2 ; DDR2               	
	(                                       	
	    print "Setting DDR2"
		d.s ASD:0xf0000000 %LE %LONG 0x0FFF1010	;ConControl	auto refresh off
		d.s ASD:0xf0000004 %LE %LONG 0x00202400	;MemControl	BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
		d.s ASD:0xf0000008 %LE %LONG 0x20E01323	;MemConfig0	512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
		d.s ASD:0xf000000C %LE %LONG 0x00E01323	;MemConfig1	
		d.s ASD:0xf0000014 %LE %LONG 0xFF000000	;PrechConfig	
		d.s ASD:0xf0000030 %LE %LONG 0x00000618	;TimingAref	7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 200MHz=0x618, 10MHz=78(0x4E)
		d.s ASD:0xf0000034 %LE %LONG 0x28233287	;TimingRow	for @200MHz
		d.s ASD:0xf0000038 %LE %LONG 0x23230304	;TimingData	CL=4
		d.s ASD:0xf000003C %LE %LONG 0x09C80232	;TimingPower
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		;d.s ASD:0xf0000034 %LE %LONG 0x16233287	;TimingRow	for @133MHz
		;d.s ASD:0xf0000038 %LE %LONG 0x23240304	;TimingData	CL=4
		;d.s ASD:0xf000003C %LE %LONG 0x09C80232	;TimingPower	
		;d.s ASD:0xf0000034 %LE %LONG 0x05111082	;TimingRow	for @25MHz
		;d.s ASD:0xf0000038 %LE %LONG 0x11140304	;TimingData	CL=4
		;d.s ASD:0xf000003C %LE %LONG 0x02C80232	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		d.s ASD:0xf0000010 %LE %LONG 0x07000000	;DirectCmd	chip0 Deselect
		d.s ASD:0xf0000010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xf0000010 %LE %LONG 0x00020000	;DirectCmd	chip0 EMRS2
		d.s ASD:0xf0000010 %LE %LONG 0x00030000	;DirectCmd	chip0 EMRS3
		d.s ASD:0xf0000010 %LE %LONG 0x00010401	;DirectCmd	chip0 EMRS1 (MEM DLL on, DQS# disable)
		d.s ASD:0xf0000010 %LE %LONG 0x00000532	;DirectCmd	chip0 MRS (MEM DLL reset) CL=4, BL=4 
		d.s ASD:0xf0000010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xf0000010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x00000432	;DirectCmd	chip0 MRS (MEM DLL unreset)(200 cycle delay ?)
		d.s ASD:0xf0000010 %LE %LONG 0x00010781	;DirectCmd	chip0 EMRS1 (OCD default)
		d.s ASD:0xf0000010 %LE %LONG 0x00010401	;DirectCmd	chip0 EMRS1 (OCD exit)
		d.s ASD:0xf0000000 %LE %LONG 0x0FF01030	;ConControl	auto refresh on
		d.s ASD:0xf0000028 %LE %LONG 0xFFFF00FF	;PwrdnConfig	
		d.s ASD:0xf0000004 %LE %LONG 0x00202413 	;MemControl	BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
	)
	
	if &DRAM_TYPE==&MCP_AC_TYPE  ; MCP A,C Type OneDram max166Mhz
	(
		print "Setting MCP_AC_TYPE"
		d.s ASD:0xf0000000 %LE %LONG 0x0FFF1010	;ConControl	auto refresh off
		d.s ASD:0xf0000004 %LE %LONG 0x00202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
		d.s ASD:0xf0000008 %LE %LONG 0x20F00222	;MemConfig0	128MB config, 4banks, Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
		d.s ASD:0xf000000C %LE %LONG 0x30F02222	;MemConfig1	
		d.s ASD:0xf0000014 %LE %LONG 0xf0000000	;PrechConfig	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;166Mhz         1Gb mDDR & 1Gb OneDRAM, 32Mx32 x1ea, ROW:14bit, COL:9bit, 4banks - for POP 166MHz  
		d.s ASD:0xf0000030 %LE %LONG 0x0000050E	;TimingAref	166MHz  = 1294(0x50E),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		d.s ASD:0xf0000034 %LE %LONG 0x14233287	;TimingRow	@166MHz
		d.s ASD:0xf0000038 %LE %LONG 0x12130005	;TimingData	CL=3
		d.s ASD:0xf000003C %LE %LONG 0x0E140222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;133Mhz
		;d.s ASD:0xf0000030 %LE %LONG 0x0000040E	;TimingAref	7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
		;d.s ASD:0xf0000034 %LE %LONG 0x10233206	;TimingRow	@133MHz
		;d.s ASD:0xf0000038 %LE %LONG 0x12130005	;TimingData	CL=3
		;d.s ASD:0xf000003C %LE %LONG 0x0E100222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;		
		d.s ASD:0xf0000010 %LE %LONG 0x07000000	;DirectCmd	chip0 Deselect
		d.s ASD:0xf0000010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xf0000010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x00000032	;DirectCmd	chip0 MRS, CL=3, BL=4
		d.s ASD:0xf0000010 %LE %LONG 0x07100000	;DirectCmd	chip1 Deselect
		d.s ASD:0xf0000010 %LE %LONG 0x01100000	;DirectCmd	chip1 PALL
		d.s ASD:0xf0000010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x00100032	;DirectCmd	chip1 MRS, CL=3, BL=4
		d.s ASD:0xf0000000 %LE %LONG 0xFF001030	;ConControl	auto refresh on
		d.s ASD:0xf0000028 %LE %LONG 0x00100002	;PwrdnConfig	
		d.s ASD:0xf0000004 %LE %LONG 0xFF212100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
	)                                       	
                                      
	if &DRAM_TYPE==&MCP_H_TYPE ; MCP H Type mDDR max200Mhz                	
	(
		print "Setting MCP_H_TYPE"
		d.s ASD:0xf0000000 %LE %LONG 0xFF001010	;ConControl	auto refresh off
		d.s ASD:0xf0000004 %LE %LONG 0x00202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
		d.s ASD:0xf0000008 %LE %LONG 0x20F01312	;MemConfig0	128MB config, 4banks ,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
		d.s ASD:0xf000000C %LE %LONG 0x30F01312	;MemConfig1	
		d.s ASD:0xf0000014 %LE %LONG 0xf0000000	;PrechConfig	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;200Mhz         1Gb mDDR & 1Gb OneDRAM, 32Mx32 x1ea, ROW:13bit, COL:10bit, 4banks - for POP 166MHz  
		d.s ASD:0xf0000030 %LE %LONG 0x00000618	;TimingAref	200MHz  = 1294(0x618),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		d.s ASD:0xf0000034 %LE %LONG 0x11344309	;TimingRow	@200MHz
		d.s ASD:0xf0000038 %LE %LONG 0x12130005	;TimingData	CL=3
		d.s ASD:0xf000003C %LE %LONG 0x0E190222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;166Mhz
		;d.s ASD:0xf0000030 %LE %LONG 0x0000050E	;TimingAref	166MHz  = 1294(0x50E),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		;d.s ASD:0xf0000034 %LE %LONG 0x0E233287	;TimingRow	@166MHz
		;d.s ASD:0xf0000038 %LE %LONG 0x12130005	;TimingData	CL=3
		;d.s ASD:0xf000003C %LE %LONG 0x0E140222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;		
		d.s ASD:0xf0000010 %LE %LONG 0x07000000	;DirectCmd	chip0 Deselect
		d.s ASD:0xf0000010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xf0000010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x00000032	;DirectCmd	chip0 MRS, CL=3, BL=4
		d.s ASD:0xf0000010 %LE %LONG 0x07100000	;DirectCmd	chip1 Deselect
		d.s ASD:0xf0000010 %LE %LONG 0x01100000	;DirectCmd	chip1 PALL
		d.s ASD:0xf0000010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xf0000010 %LE %LONG 0x00100032	;DirectCmd	chip1 MRS, CL=3, BL=4
		d.s ASD:0xf0000000 %LE %LONG 0xFF001030	;ConControl	auto refresh on
		d.s ASD:0xf0000028 %LE %LONG 0x00100002	;PwrdnConfig	
		d.s ASD:0xf0000004 %LE %LONG 0xff202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
	)      
	print "DRAM Port0 Initialization done..."
)

if &DRAM_INIT==&DMC_en
(
	print "SDRAM DMC1 Initialization"
	
	;;; dll enable
	d.s ASD:0xF1400018 %LE %LONG 0x00101000	;PhyControl0	DLL parameter setting
	d.s ASD:0xF140001C %LE %LONG 0x00000086	;PhyControl1	DLL parameter setting
	;;d.s ASD:0xF1400020 %LE %LONG 0x00000000	;PhyControl2	DLL parameter setting
	d.s ASD:0xF1400018 %LE %LONG 0x00101002	;PhyControl0	DLL on
	d.s ASD:0xF1400018 %LE %LONG 0x00101003	;PhyControl0	DLL을 start 시킴
	;;;d.s ASD:0xF1400040 %LE %LONG 0xXXXXXXX3	;PhyStatus0	DLL이 locking 되었는지 check
	wait 0.2s
	;;; DLL off Case
	d.s ASD:0xF1400018 %LE %LONG 0x71101003	;PhyControl0	DLL off시를 위해 locking value 를 forcing 시킴
	d.s ASD:0xF1400018 %LE %LONG 0x71101009	;PhyControl0	DLL off

	;;; dll disable
	;d.s ASD:0xF1400018 %LE %LONG 0x00000000	;PhyControl0	DLL parameter setting
	;d.s ASD:0xF140001C %LE %LONG 0x00000000	;PhyControl1	DLL parameter setting
	;d.s ASD:0xF1400020 %LE %LONG 0x00000000	;PhyControl2	DLL parameter setting

	if &DRAM_TYPE==&DDR2 ; DDR2               	
	(                                       	
		print "Setting DDR2"
		d.s ASD:0xf1400000 %LE %LONG 0x0FFF1010	;ConControl	auto refresh off
		d.s ASD:0xf1400004 %LE %LONG 0x00202400	;MemControl	BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
		;;;DDR2 2G Setting
		d.s ASD:0xf1400008 %LE %LONG 0x40C01333	;MemConfig0	1024MB config, 8 banks, 1:linterleaved, DMC1 evt1(0x40~0x7f)
		d.s ASD:0xf140000C %LE %LONG 0x00C01333	;MemConfig1
		;;;DDR2 1G Setting
		;d.s ASD:0xf1400008 %LE %LONG 0x40E01323	;MemConfig0	512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
		;d.s ASD:0xf140000C %LE %LONG 0x00E01323	;MemConfig1			
		d.s ASD:0xf1400014 %LE %LONG 0xFF000000	;PrechConfig	
		d.s ASD:0xf1400030 %LE %LONG 0x00000618	;TimingAref	7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 200MHz=0x618
		d.s ASD:0xf1400034 %LE %LONG 0x28233289	;TimingRow	for @200MHz
		d.s ASD:0xf1400038 %LE %LONG 0x23230304	;TimingData	CL=3
		d.s ASD:0xf140003C %LE %LONG 0x08280232	;TimingPower
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		;d.s ASD:0xf1400034 %LE %LONG 0x16233287	;TimingRow	for @133MHz
		;d.s ASD:0xf1400038 %LE %LONG 0x23240304	;TimingData	CL=4
		;d.s ASD:0xf140003C %LE %LONG 0x09C80232	;TimingPower	
		;d.s ASD:0xf1400034 %LE %LONG 0x05111082	;TimingRow	for @25MHz
		;d.s ASD:0xf1400038 %LE %LONG 0x11140304	;TimingData	CL=4
		;d.s ASD:0xf140003C %LE %LONG 0x02C80232	;TimingPower
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
		d.s ASD:0xf1400010 %LE %LONG 0x07000000	;DirectCmd	chip0 Deselect
		d.s ASD:0xf1400010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xf1400010 %LE %LONG 0x00020000	;DirectCmd	chip0 EMRS2
		d.s ASD:0xf1400010 %LE %LONG 0x00030000	;DirectCmd	chip0 EMRS3
		d.s ASD:0xf1400010 %LE %LONG 0x00010401	;DirectCmd	chip0 EMRS1 (MEM DLL on, DQS# disable)
		d.s ASD:0xf1400010 %LE %LONG 0x00000532	;DirectCmd	chip0 MRS (MEM DLL reset) CL=3, BL=4
		d.s ASD:0xf1400010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xf1400010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf1400010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xf1400010 %LE %LONG 0x00000432	;DirectCmd	chip0 MRS (MEM DLL unreset)(200 cycle delay ?)
		d.s ASD:0xf1400010 %LE %LONG 0x00010781	;DirectCmd	chip0 EMRS1 (OCD default)
		d.s ASD:0xf1400010 %LE %LONG 0x00010401	;DirectCmd	chip0 EMRS1 (OCD exit)
		d.s ASD:0xf1400000 %LE %LONG 0x0FF01030	;ConControl	auto refresh on
		d.s ASD:0xf1400028 %LE %LONG 0xFFFF00FF	;PwrdnConfig	
		d.s ASD:0xf1400004 %LE %LONG 0x00202413 	;MemControl	BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
    )	
	
	if &DRAM_TYPE==&MCP_AC_TYPE  ; MCP A,C Type mDDR max200Mhz
	(
		print "Setting MCP_AC_TYPE"
		d.s ASD:0xF1400000 %LE %LONG 0xFF001010	;ConControl	auto refresh off
		d.s ASD:0xF1400004 %LE %LONG 0x00202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
		d.s ASD:0xF1400008 %LE %LONG 0x40F81222	;MemConfig0	128MB config, 4banks, ,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
		d.s ASD:0xF140000C %LE %LONG 0x50F81222	;MemConfig1	
		d.s ASD:0xF1400014 %LE %LONG 0xF0000000	;PrechConfig	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;200Mhz         1Gb mDDR & 1Gb OneDRAM, 32Mx32 x1ea, ROW:13bit, COL:10bit, 4banks - for POP 166MHz  
		d.s ASD:0xF1400030 %LE %LONG 0x00000618	;TimingAref	200MHz  = 1294(0x618),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		d.s ASD:0xF1400034 %LE %LONG 0x11344309	;TimingRow	@200MHz
		d.s ASD:0xF1400038 %LE %LONG 0x12130005	;TimingData	CL=3
		d.s ASD:0xF140003C %LE %LONG 0x0E190222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;166Mhz
		;d.s ASD:0xF1400030 %LE %LONG 0x0000050E	;TimingAref	166MHz  = 1294(0x50E),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		;d.s ASD:0xF1400034 %LE %LONG 0x0E233287	;TimingRow	@166MHz
		;d.s ASD:0xF1400038 %LE %LONG 0x12130005	;TimingData	CL=3
		;d.s ASD:0xF140003C %LE %LONG 0x0E140222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;		
		d.s ASD:0xF1400010 %LE %LONG 0x07000000	;DirectCmd	chip0 Deselect
		d.s ASD:0xF1400010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xF1400010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x00000032	;DirectCmd	chip0 MRS, CL=3, BL=4
		d.s ASD:0xF1400010 %LE %LONG 0x07100000	;DirectCmd	chip1 Deselect
		d.s ASD:0xF1400010 %LE %LONG 0x01100000	;DirectCmd	chip1 PALL
		d.s ASD:0xF1400010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x00100032	;DirectCmd	chip1 MRS, CL=3, BL=4
		d.s ASD:0xF1400000 %LE %LONG 0xFF001030	;ConControl	auto refresh on
		d.s ASD:0xF1400028 %LE %LONG 0x00100002	;PwrdnConfig	
		d.s ASD:0xF1400004 %LE %LONG 0x00202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
	)                                       	
                                      
	if &DRAM_TYPE==&MCP_H_TYPE ; MCP H Type mDDR max200Mhz                	
	(
		print "Setting MCP_H_TYPE"
		d.s ASD:0xF1400000 %LE %LONG 0xFF001010	;ConControl	auto refresh off
		d.s ASD:0xF1400004 %LE %LONG 0x00202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
		d.s ASD:0xF1400008 %LE %LONG 0x40F81312	;MemConfig0	128MB config, 4banks, ,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
		d.s ASD:0xF140000C %LE %LONG 0x50F81312	;MemConfig1	
		d.s ASD:0xF1400014 %LE %LONG 0xF0000000	;PrechConfig	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;200Mhz         1Gb mDDR & 1Gb OneDRAM, 32Mx32 x1ea, ROW:13bit, COL:10bit, 4banks - for POP 166MHz  
		d.s ASD:0xF1400030 %LE %LONG 0x00000618	;TimingAref	200MHz  = 1294(0x618),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		d.s ASD:0xF1400034 %LE %LONG 0x11344309	;TimingRow	@200MHz
		d.s ASD:0xF1400038 %LE %LONG 0x12130005	;TimingData	CL=3
		d.s ASD:0xF140003C %LE %LONG 0x0E190222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;166Mhz
		;d.s ASD:0xF1400030 %LE %LONG 0x0000050E	;TimingAref	166MHz  = 1294(0x50E),7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C)
		;d.s ASD:0xF1400034 %LE %LONG 0x0E233287	;TimingRow	@166MHz
		;d.s ASD:0xF1400038 %LE %LONG 0x12130005	;TimingData	CL=3
		;d.s ASD:0xF140003C %LE %LONG 0x0E140222	;TimingPower	
		;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;		
		d.s ASD:0xF1400010 %LE %LONG 0x07000000	;DirectCmd	chip0 Deselect
		d.s ASD:0xF1400010 %LE %LONG 0x01000000	;DirectCmd	chip0 PALL
		d.s ASD:0xF1400010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x05000000	;DirectCmd	chip0 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x00000032	;DirectCmd	chip0 MRS, CL=3, BL=4
		d.s ASD:0xF1400010 %LE %LONG 0x07100000	;DirectCmd	chip1 Deselect
		d.s ASD:0xF1400010 %LE %LONG 0x01100000	;DirectCmd	chip1 PALL
		d.s ASD:0xF1400010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x05100000	;DirectCmd	chip1 REFA
		d.s ASD:0xF1400010 %LE %LONG 0x00100032	;DirectCmd	chip1 MRS, CL=3, BL=4
		d.s ASD:0xF1400000 %LE %LONG 0xFF001030	;ConControl	auto refresh on
		d.s ASD:0xF1400028 %LE %LONG 0x00100002	;PwrdnConfig	
		d.s ASD:0xF1400004 %LE %LONG 0x00202100	;MemControl	BL=4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off
	)      

	
	print "DRAM Port1 Initialization done..."
)
	
	print "DRAM Initialization done..."


